Year
Tech & Technique
Description
Image Interpolation ASIP is a custom processor (Application-Specific Instruction Set Processor) developed to perform bilinear interpolation on grayscale images. The processor uses a custom-designed ISA (instruction set architecture) named MEMS, built specifically for this project. The processor is implemented in SystemVerilog, runs on an FPGA Terasic DE1-SoC, and supports pipelining, memory segmentation, and user interaction through physical peripherals (keyboard). Input images and results are displayed via VGA. This project was developed in the context of a computer architecture course to apply real-world processor design, custom ISA creation, and image manipulation using low-level hardware techniques.
My Role
As part of a team, my responsibilities on that project were: ,
- Design the custom ISA to be used in the ASIP to interpolate images.
- Model the architectural diagrams to build the processor that will run on the FPGA.
- Developed test benches for each section of the processor, including the pipeline.